Heat dissipation for wire-bonded microelectronic components typically employs a metal slug disposed over the silicon die (chip). FIG. 1 illustrates a wire-bonded device in accordance with the prior art. Device 100, shown in FIG. 1, includes a chip 105 wire-bonded to substrate 110 with wire-bonds 106. The chip 105 may be silicon or some other semiconductor material. During operation, heat is produced, which must be removed from the chip. The substrate 110 may typically be made of ceramic or some type of organic packaging. The substrate 110 is disposed upon a printed circuit board (PCB) (motherboard), not shown.
The heat is removed through a thermal slug 115, which is typically a highly thermally conductive metal such as copper or aluminum. Typically, the thermal slug 115 may be T-shaped to accommodate the wire-bonds 106 as shown. Alternatively, the thermal slug may simply be sized to cover only the inner portion of the chip 105 thereby avoiding the wire-bonds 106. The chip 105 and wire-bonds 106 may then be protected by an encapsulate 120 (typically plastic) applied over the surface of the substrate 110. A heat sink, not shown, may be attached to the thermal slug to increase heat removal capability. Additionally or alternatively, a fan may be directed over the thermal slug.
This heat removal scheme has the disadvantage that the majority of heat removal is taking place from the top of the chip. The top side of the chip may not be the hottest side, depending on where the components are located within the chip. This means the heat is drawn through the upper components of the chip to the thermal slug.
Additional difficulties arise for stacked-chip configurations. Over the past several years there has been some interest in stacking chips where possible. One such chip-stacking scheme stacks a number of decreasing sized chips in order to facilitate the wire-bonds. FIG. 1 A illustrates a stacked-chip device in accordance with the prior art. The stacked-chip device 150 includes a number of successively smaller chips 155–157 stacked atop one another and wire-bonded to a substrate 160. As illustrated in FIG. 1A, the area over which heat slug 165 contacts chip 157 is relatively small compared to the single chip scheme of FIG. 1. Moreover, the increased number of chips produces increased heat, which must be drawn across an even greater distance. That is, much of the heat produced by chip 155 has to be drawn through chips 156 and 157 to the heat slug 165. This applies equally even to stacked-chip schemes that employ methods for stacking same-sized chips (e.g., beveling or intermediate spacers).
Another disadvantage of such schemes is that the coefficient of thermal expansion (CTE) of the heat slug (typically a highly thermally conductive metal) and that of the semiconductor chip (e.g., silicon) are different. Such a mismatch in CTE may result in warping the chip during expected temperature changes that occur during normal operation. This necessitates a thermal interface material (TIM) layer (not shown) between the heat slug and the chip. Inclusion of a TIM layer increases the fabrication process steps and because the TIM layer has its own thermal resistance, reduces the heat removal capability of the device.
Currently, typical stacked-chip designs are used for stacking memory chips, which are relatively low wattage. However, as the number of chips in a stacked-chip device increases, it will be more and more difficult to remove the heat from such devices using the configuration illustrated in FIG. 1A.
Moreover, it may be desirable to stack higher-powered chips (e.g., processors), exclusively or in combination with memory chips. For such designs, the current heat removal schemes will most likely prove inadequate.